library ieee;
use ieee.std_logic_1164.all;

entity pract4 is
port(A,B,C,D :in std_logic;
	H:out std_logic);
	
end pract4;


architecture bhv of pract4 is
begin

H <= ((A and B) xor (B and C)) or (not((B and C) xor (not(C and D))));

end bhv;